The present invention relates to an interrupt control method for a multiprocessor system, and more particularly, to an interrupt control method for a multiprocessor system, which enables each processor to recognize an interrupt without using a special interrupt control line.
As systems employing processors become more and more sophisticated and complex, multiprocessor systems are used wherein a plurality of processors is used in a single system. In such a multiprocessor system, the processors employed are interconnected by a bus. For effecting an external interrupt, therefore, each processor requires a special dedicated line for interrupts. The more CPUs used, the more such special interrupt lines are needed, resulting in increased hardware and lowered system flexibility.